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职位名称 职位类型 工作地点 操作
作为ASIC IP Verification团队的一员,你将会负责以下工作内容(但不限于此):

- 准备模块级、IP级的验证架构文档
- 从模块到系统开发各级Testbench,准备test plan
- 继续并跟踪各种验证任务和进度
- 优化验证流程,采用各种验证方法和工具保证功能正确
- 参与模块级或者系统级的测试,比如FPGA或者硬件仿真加速器
- 交叉检查设计文档,验证代码,和覆盖率等任务

职位要求: 
- 电子、信息工程、通讯、计算机、自动化,或其他相关专业
- 掌握任何一项验证技能:SystemVerilog, UVM, Assertion, Coverage等等
- 熟悉Verilog或者SystemVerilog和Script语言,比如Shell, Perl, Python
- 自我驱动,自我激励,热爱学习,愿意接受挑战

如有以下一项或者多项知识是加分项:
- 有验证环境搭建经验,包括SV/UVM/C/C++
- 有大型IP(AI/NPU/GPU/CPU/ISP)或者SOC实际项目验证经验
- 理解或熟悉汇编语言(ARM/RISCV/MIPS),理解或熟悉C/C++语言
- 有计算机体系结构知识,比如ARM, RISCV,或MIPS的内核和Cache、TCM
- 深度神经网络知识,比如流行的Framework/Network,相关的硬件加速器
- 熟悉或者了解ARM AMBA 总线协议,包括 AXI/AHB/APB,或者Tilelink
- 做过低功耗验证


职位要求: 
- 电子、信息工程、通讯、计算机、自动化,或其他相关专业
- 掌握任何一项验证技能:SystemVerilog, UVM, Assertion, Coverage等等
- 熟悉Verilog或者SystemVerilog和Script语言,比如Shell, Perl, Python
- 自我驱动,自我激励,热爱学习,愿意接受挑战

如有以下一项或者多项知识是加分项:
- 有验证环境搭建经验,包括SV/UVM/C/C++
- 有大型IP(AI/NPU/GPU/CPU/ISP)或者SOC实际项目验证经验
- 理解或熟悉汇编语言(ARM/RISCV/MIPS),理解或熟悉C/C++语言
- 有计算机体系结构知识,比如ARM, RISCV,或MIPS的内核和Cache、TCM
- 深度神经网络知识,比如流行的Framework/Network,相关的硬件加速器
- 熟悉或者了解ARM AMBA 总线协议,包括 AXI/AHB/APB,或者Tilelink
- 做过低功耗验证


工作内容:      
作为ASIC IP Verification团队的一员,你将会负责以下工作内容(但不限于此):

- 准备模块级、IP级的验证架构文档
- 从模块到系统开发各级Testbench,准备test plan
- 继续并跟踪各种验证任务和进度
- 优化验证流程,采用各种验证方法和工具保证功能正确
- 参与模块级或者系统级的测试,比如FPGA或者硬件仿真加速器
- 交叉检查设计文档,验证代码,和覆盖率等任务

职位要求: 
- 电子、信息工程、通讯、计算机、自动化,或其他相关专业
- 掌握任何一项验证技能:SystemVerilog, UVM, Assertion, Coverage等等
- 熟悉Verilog或者SystemVerilog和Script语言,比如Shell, Perl, Python
- 自我驱动,自我激励,热爱学习,愿意接受挑战

如有以下一项或者多项知识是加分项:
- 有验证环境搭建经验,包括SV/UVM/C/C++
- 有大型IP(AI/NPU/GPU/CPU/ISP)或者SOC实际项目验证经验
- 理解或熟悉汇编语言(ARM/RISCV/MIPS),理解或熟悉C/C++语言
- 有计算机体系结构知识,比如ARM, RISCV,或MIPS的内核和Cache、TCM
- 深度神经网络知识,比如流行的Framework/Network,相关的硬件加速器
- 熟悉或者了解ARM AMBA 总线协议,包括 AXI/AHB/APB,或者Tilelink
- 做过低功耗验证

工作内容:      
作为ASIC IP Design团队的一员,你将会负责以下工作内容(但不限于此):

- 准备模块级、IP级、芯片级的微架构 
- 模块级或子系统级的算法或功能逻辑的RTL实现
- 网表产生和交付,包括Lint、CDC、综合/DCG等等
- 第三方IP的配置、优化,和性能、功能系统集成
- 帮助后端团队进行PR实现和时序分析
- 帮助系统、验证、Bring-up团队做功能和性能的系统测试

职位要求:  
- 电子、信息工程、通讯、计算机、自动化,或其他相关专业
- 良好的计算机体系结构知识
- 熟悉Verilog或者SystemVerilog.
- 对ASIC前端设计流程有一定的实际经验或知识 
- 自我驱动,自我激励,热爱学习

如有以下一项或者多项是加分项:
- 计算机体系结构知识,比如ARM, RISCV,或MIPS的内核和Cache、TCM.
- FPGA或者IC加速器的实现经验,包括AI/NPU、GPU、ISP、Video、或者通讯系统
- 深度神经网络知识,比如流行的Framework/Network,相关的硬件加速器
- 有大型SOC 系统经验或知识,有完整项目经验
- 有任意以下任务经验:RTL Lint/CDC检查,时序约束产生,综合,形式验证,时序检查
- 熟悉ARM AMBA 总线协议,包括 AXI/AHB/APB, 或者TileLink
- 低功耗实现和经验,包括Clock Gating、多电压域设计和UPF产生

工作内容:      
作为ASIC IP Design团队的一员,你将会负责以下工作内容(但不限于此):

- 准备模块级、IP级、芯片级的微架构 
- 模块级或子系统级的算法或功能逻辑的RTL实现
- 网表产生和交付,包括Lint、CDC、综合/DCG等等
- 第三方IP的配置、优化,和性能、功能系统集成
- 帮助后端团队进行PR实现和时序分析
- 帮助系统、验证、Bring-up团队做功能和性能的系统测试

职位要求:  
- 电子、信息工程、通讯、计算机、自动化,或其他相关专业
- 良好的计算机体系结构知识
- 熟悉Verilog或者SystemVerilog.
- 对ASIC前端设计流程有一定的实际经验或知识 
- 自我驱动,自我激励,热爱学习

如有以下一项或者多项是加分项:
- 计算机体系结构知识,比如ARM, RISCV,或MIPS的内核和Cache、TCM.
- FPGA或者IC加速器的实现经验,包括AI/NPU、GPU、ISP、Video、或者通讯系统
- 深度神经网络知识,比如流行的Framework/Network,相关的硬件加速器
- 有大型SOC 系统经验或知识,有完整项目经验
- 有任意以下任务经验:RTL Lint/CDC检查,时序约束产生,综合,形式验证,时序检查
- 熟悉ARM AMBA 总线协议,包括 AXI/AHB/APB, 或者TileLink
- 低功耗实现和经验,包括Clock Gating、多电压域设计和UPF产生

工作内容:      
作为ASIC IP Design团队的一员,你将会负责以下工作内容(但不限于此):

- 准备模块级、IP级、芯片级的微架构 
- 模块级或子系统级的算法或功能逻辑的RTL实现
- 网表产生和交付,包括Lint、CDC、综合/DCG等等
- 第三方IP的配置、优化,和性能、功能系统集成
- 帮助后端团队进行PR实现和时序分析
- 帮助系统、验证、Bring-up团队做功能和性能的系统测试

职位要求:  
- 电子、信息工程、通讯、计算机、自动化,或其他相关专业
- 良好的计算机体系结构知识
- 熟悉Verilog或者SystemVerilog.
- 对ASIC前端设计流程有一定的实际经验或知识 
- 自我驱动,自我激励,热爱学习

如有以下一项或者多项是加分项:
- 计算机体系结构知识,比如ARM, RISCV,或MIPS的内核和Cache、TCM.
- FPGA或者IC加速器的实现经验,包括AI/NPU、GPU、ISP、Video、或者通讯系统
- 深度神经网络知识,比如流行的Framework/Network,相关的硬件加速器
- 有大型SOC 系统经验或知识,有完整项目经验
- 有任意以下任务经验:RTL Lint/CDC检查,时序约束产生,综合,形式验证,时序检查
- 熟悉ARM AMBA 总线协议,包括 AXI/AHB/APB, 或者TileLink
- 低功耗实现和经验,包括Clock Gating、多电压域设计和UPF产生


Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the FPGA prototyping and SoC validation work for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to be working closely with SoC design/verification, platform design and validation team and work out the solution including the FPGA prototyping, emulation and simulation to validate our SoC.

The engineer will be working in the SiEngine R&D SW/VI team.

Main Responsibility:
- FPGA functional design with Verilog or VHDL
- FPGA simulation and verification strategy planning and architecture design
- Porting ASIC to Z1/Zebu platform and provide support and maintain
- Porting ASIC to FPGA, generate/run/debug test cases on FPGA
- Build up and maintain FPGA test platforms, including PCB schematic design and layout support

Required Skills:

- More than 2 years working experience on FPGA design and verification
- Good Knowledge on FPGA design process, knowledge on verification methodology, UVM is a plus
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Familiar with System Verilog, VHDL is a plus
- Be familiar with any standard HW protocol and interfaces and IO standards such as PCIe, MIPI CSI/DSI, DP, SERDES, I2C, SGMII, USB, DDR, AMBA, EBI, EMIF, RapidIO.
- Familiar with board design and schematic
- Good experience in using high-speed oscilloscope, logic analyzer or other protocol analyzer.
- Experience in VCS/Palladium Z1/X1/Zebu/FPGA/Trace32 is a plus.
- Familiar with Git/Gerrit source code management tool.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the FPGA prototyping and SoC validation work for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to be working closely with SoC design/verification, platform design and validation team and work out the solution including the FPGA prototyping, emulation and simulation to validate our SoC.

The engineer will be working in the SiEngine R&D SW/VI team.


Main Responsibility:
- FPGA functional design with Verilog or VHDL
- FPGA simulation and verification strategy planning and architecture design
- Porting ASIC to Z1/Zebu platform and provide support and maintain
- Porting ASIC to FPGA, generate/run/debug test cases on FPGA
- Build up and maintain FPGA test platforms, including PCB schematic design and layout support

Required Skills:

- More than 2 years working experience on FPGA design and verification
- Good Knowledge on FPGA design process, knowledge on verification methodology, UVM is a plus
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Familiar with System Verilog, VHDL is a plus
- Be familiar with any standard HW protocol and interfaces and IO standards such as PCIe, MIPI CSI/DSI, DP, SERDES, I2C, SGMII, USB, DDR, AMBA, EBI, EMIF, RapidIO.
- Familiar with board design and schematic
- Good experience in using high-speed oscilloscope, logic analyzer or other protocol analyzer.
- Experience in VCS/Palladium Z1/X1/Zebu/FPGA/Trace32 is a plus.
- Familiar with Git/Gerrit source code management tool.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the software development of Linux kernel driver and user space reference application for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to design and work out the solution from the Linux kernel device driver, SDK and the reference application.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the bootloader, Linux kernel driver and test application for the SiEngine automotive SoC.
- Develop the software to enable and validate the driver.
- Build the automation validation framework (SLT) to validate/test the SoC and Linux.
- Develop the board support package and the reference application.

Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in writing low-level software that interacts directly with hardware.
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Good experience in Linux driver development is a must.
- Good experience in using/customizing the opensource software.
- Familiar with bootloader such as ARM trusted firmware, u-boot etc.
- Experience in open source software such as buildroot, yacto, busybox, etc.
- Experience in LSIO driver such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.
- Experience in Linux kernel memory management, power management (DVFS, PSCI, STR) is a plus.
- Experience in HSIO driver such as PCIE/USB2/USB3/ETH/V2L4(CSI)/UFS/DRM(DSI, DP) is a big plus.
- Familiar with Git/Gerrit source code management tool.
- Familiar with scripts such as bash, python, etc.
- Excellent communication skills, good teamwork adaptability, self-motivated.


Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the software development of Linux kernel driver and user space reference application for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to design and work out the solution from the Linux kernel device driver, SDK and the reference application.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the bootloader, Linux kernel driver and test application for the SiEngine automotive SoC.
- Develop the software to enable and validate the driver.
- Build the automation validation framework (SLT) to validate/test the SoC and Linux.
- Develop the board support package and the reference application.

Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in writing low-level software that interacts directly with hardware.
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Good experience in Linux driver development is a must.
- Good experience in using/customizing the opensource software.
- Familiar with bootloader such as ARM trusted firmware, u-boot etc.
- Experience in open source software such as buildroot, yacto, busybox, etc.
- Experience in LSIO driver such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.
- Experience in Linux kernel memory management, power management (DVFS, PSCI, STR) is a plus.
- Experience in HSIO driver such as PCIE/USB2/USB3/ETH/V2L4(CSI)/UFS/DRM(DSI, DP) is a big plus.
- Familiar with Git/Gerrit source code management tool.
- Familiar with scripts such as bash, python, etc.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the development of AI SDK framework software on the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to develop the NN inference framework on Android or embedded Linux platform based on the SiEngine Soc.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the NN inference  framework on Android, which is integrated with NN API.
- Develop the NN inference framework on embedded Linux.
- Develop the NPU, GPU, CPU backend running driver for NN inference framework.
- Work closely with the AI Application software engineer to extend the NN compute operator.

Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in Android NDK, HAL development work, or embedded Linux Midware development work.
- Solid knowledge on ARM architectures (Core: A, R or M)
- Solid programming skill in C/C++ (above C++ 11).
- Good experience in C++ big project development.
- Good knowledge in NPU GPU, CPU SIMD parallel computing is required.
- Familiar with OpenCL, OpenVX, Neon parallel programming for NPU, GPU, CPU
- Experience in deep learning framework, like TensorFlow/PyTorch/Caffe is good plus.
- Experience in machine learning/deep learning algorithms is plus.

- Knowledge in FuSa ISO 26262 is plus.
- Familiar with Git/Gerrit source code management tool.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the development of AI SDK framework software on the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to develop the NN inference framework on Android or embedded Linux platform based on the SiEngine Soc.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the NN inference  framework on Android, which is integrated with NN API.
- Develop the NN inference framework on embedded Linux.
- Develop the NPU, GPU, CPU backend running driver for NN inference framework.
- Work closely with the AI Application software engineer to extend the NN compute operator.


Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in Android NDK, HAL development work, or embedded Linux Midware development work.
- Solid knowledge on ARM architectures (Core: A, R or M)
- Solid programming skill in C/C++ (above C++ 11).
- Good experience in C++ big project development.
- Good knowledge in NPU GPU, CPU SIMD parallel computing is required.
- Familiar with OpenCL, OpenVX, Neon parallel programming for NPU, GPU, CPU
- Experience in deep learning framework, like TensorFlow/PyTorch/Caffe is good plus.
- Experience in machine learning/deep learning algorithms is plus.

- Knowledge in FuSa ISO 26262 is plus.
- Familiar with Git/Gerrit source code management tool.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the board enablement and SoC validation work for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to be working closely with SoC design/verification, platform design and product team and work out the solution from the bare-metal, device driver to automation framework to validate our SoC.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the bare metal driver to bringup and validate the SiEngine automotive SoC.
- Develop the software to enable and validate the development boards.
- Build the automation validation framework (SLT) to validate/test the SoC.
- Develop the tools for the SoC and board manufacture.
- Evaluate the power/current/frequency of SoC with the different corner(skew) chips

Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in writing low-level software that interacts directly with hardware.
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Experience in driver development or experience in Linux driver development is a plus.
- Familiar with bootloader, Linux and any RTOS
- Familiar with board design and schematic
- Good experience in using high-speed oscilloscope, logic analyzer or other protocol analyzer.
- Experience in LSIO such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.
- Experience in VCS/Palladium Z1/X1/Zebu/FPGA/Trace32/System Verilog/UVM is a plus.
- Experience in HSIO such as DDR/PCIE/USB/ETH/MIPI (CSI, DSI)/UFS/DP is a big plus.
- Familiar with Git/Gerrit source code management tool.
- Familiar with scripts such as bash, python, etc.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Position Description:

The SiEngine technology is co-funded by Geely Group and ARM China Company. This position will be responsible for the board enablement and SoC validation work for the ARM based processor targeting the market of the automotive SoC solution.  The candidate is required to be working closely with SoC design/verification, platform design and product team and work out the solution from the bare-metal, device driver to automation framework to validate our SoC.

The engineer will be working in the SiEngine R&D SW team.


Main Responsibility:
- Develop the bare metal driver to bringup and validate the SiEngine automotive SoC.
- Develop the software to enable and validate the development boards.
- Build the automation validation framework (SLT) to validate/test the SoC.
- Develop the tools for the SoC and board manufacture.
- Evaluate the power/current/frequency of SoC with the different corner(skew) chips

Required Skills:

- 5+ years of software development in automotive, embedded system or mobile.
- At least 2-years of experience in writing low-level software that interacts directly with hardware.
- Solid knowledge on ARM architectures (Core: A, R or M, MMU, SMMU, GIC, Interconnection)
- Experience in driver development or experience in Linux driver development is a plus.
- Familiar with bootloader, Linux and any RTOS
- Familiar with board design and schematic
- Good experience in using high-speed oscilloscope, logic analyzer or other protocol analyzer.
- Experience in LSIO such as UART/I2C/SPI/GPIO/PWM/SD/MMC is preferred.
- Experience in VCS/Palladium Z1/X1/Zebu/FPGA/Trace32/System Verilog/UVM is a plus.
- Experience in HSIO such as DDR/PCIE/USB/ETH/MIPI (CSI, DSI)/UFS/DP is a big plus.
- Familiar with Git/Gerrit source code management tool.
- Familiar with scripts such as bash, python, etc.
- Excellent communication skills, good teamwork adaptability, self-motivated.

Education Requirement:

- B. Sc. or above degree from China top universities with major on Computer Science, EE or Automation etc.

Job Description
As part of the SoC design team, engineer will mainly focus on following areas, but not limited to:
-Prepare micro-architecture specification for IP, subsystem or chip;
-RTL implementation and perform integration into SOCs.
-3rd party IP configuration , optimization
-Subsystem design with in-house design and 3rd party IP
-Subsystem implementation, including synthesis/linting/cdc/DCG flow/…
-Assist with backend team on perform place-and-route and timing analysis of modules
-Assist with chip bring up and perform silicon functional/performance validation.

Job Requirement
- M.Sc. or Ph.D. degree in electrical engineering, computer engineering or equal
- Good background in C, Verilog, SystemVerilog and verification methodology.
- A high-level of self-motivation and a proactive approach to solving problems

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